ASIC Design Engineer (MJ0... 15k-20k

Responsibilities:
1. Contribute to chip- and block-level architecture specification.
2. Implement RTL in Verilog/System Verilog.
3. Perform RTL and gate-level simulation/verification.
4. Drive synthesis and timing closure.
Collaborate with cross-functional teams to deliver tape-out.


Qualifications:
1. Bachelor’s degree or above in IC, microelectronics, optoelectronics, telecommunications, etc.
2. Solid digital-design fundamentals, fluent in Verilog/System Verilog.
3. Hands-on experience with EDA tools and full IC design flow.
4. Proficient in Tcl/Shell/Perl/Python scripting.
5. Fast learner, able to solve problems independently, strong team player.Excellent written and spoken English.