DFT Engineer (MJ000062) 15k-20k

Responsibilities :
1. Own DFT architecture and implementation for scan, memory BIST and boundary scan.
2. Verify DFT logic at both RTL and gate level.
3. Generate CP/ATE test patterns and support silicon debug on the tester.
4. Build and maintain automated DFT design & verification flows.
5. Perform synthesis, STA and formal verification for DFT modes.
Perform logic BIST, memory BIST and scan based diagnosis to improve yield.


Qualifications:
1. Bachelor’s degree or higher in IC, Microelectronics, Optoelectronics, Telecommunications, etc.
2. Solid understanding of synthesis and timing closure.
3. Solid understanding of IPs, integration and verification.
4. Team spirit and strong communication skills.
5. Enjoy challenging work and a Self-motivated good team player.
6. Good English communication skills are preferred.
7. Experience in Perl, TCL, and Shell scripting is preferred.
Hands-on experience with Synopsys (DFT Compiler/TetraMax) or Mentor Tessent is preferred.