数字ic验证工程师 30k-40k

Requirements:
The candidate is preferred to be MSEE with minimum of 5+ years, in digital ASIC/SOC design verification.
The candidate should have good understanding on ASIC/SOC design flow and should have:
1. Familiar with one of major verification languages: UVM, C, C++, System Verilog, Verilog
2. Good knowledge of design verification methodology, such as UVM or OVM and coverage driven verification methodology
3. Many experiences with simulation model creation and the testbench build
4. Strong RTL coding with Verilog and familiar with front-end design flow
5. Background in one of the area below will be a strong plus: a. Strong C/C++ software development experiences for ARM based SoC system b. Video, display, GPU, DDR, PCIe, USB etc.. 6. Be familiar with scripting language, such as Perl, C shell, Makefile.